| - |
- | - | EEIF | WRERR | WREN | WR | RD |
|---|---|---|---|---|---|---|---|
| 7 |
6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 7-6-5 |
- | Not implemented, Read as 0. |
|---|---|---|
| 4 |
EEIF | 1: Write is complete (must be cleared by software). 0: The write operation is not complete or has not been started. |
| 3 |
WRERR | 1:A write operation is prematurely terminated
(any MCLR Reset or any WDT Reset during normal operation). 0:The write operation completed. |
| 2 |
WREN | 1:Allows write cycles. 0:Inhibits write to the EEPROM. |
| 1 |
WR | 1:Initiates a write cycle. The bit is cleared by hardware once write is complete. The WR bit
can only be set (not cleared) in software. 0:Write cycle to the EEPROM is complete. |
| 0 |
RD | 1:Initiates an EEPROM read RD is cleared in hardware. The RD bit can only be set (not
cleared) in software.
0:Does not initiate an EEPROM read |