| Keyword | Address/Number | Description |
|---|---|---|
| TMR0 | 0X01 | Register holding TIMER 0 value |
| PCL | 0C02 | Program Counter Low Byte |
| STATUS | 0X03 | |
| FSR | 0X04 | |
| PORTA | 0X05 | |
| PORTB | 0X06 | |
| PCLATH | 0X0A | Program Counter High Byte |
| INTCON | 0X0B | Interrupt Control Register |
| PIR1 | 0X0C | Peripheral Interrupt Register |
| TMR1L | 0X0E | |
| TMR1H | 0X0F | |
| T1CON | 0X10 | Timer 1 Control Register |
| TMR2 | 0X11 | |
| T2CON | 0X12 | Timer 2 Control Register |
| CCP1L | 0X15 | |
| CCP1H | 0X16 | |
| CCP1CON | 0X17 | CCP Operation Register |
| RCSTA | 0X18 | Receive Status and Control Register |
| TXREG | 0X19 | |
| RCREG | 0X1A | |
| CMCON | 0X1F | Comparator Configuration Register |
| OPTION_REG | 0X81 | Option Register |
| TRISA | 0X85 | |
| TRISB | 0X86 | |
| PIE1 | 0X8C | Peripheral Interrupt Enable Register |
| PCON | 0X8E | Power Control Register |
| PR2 | 0X92 | |
| TXSTA | 0X98 | Transmit Status and Control Register |
| SPBRG | 0X99 | |
| EEDATA | 0X9A | |
| EEADR | 0X9B | |
| EECON1 | 0X9C | |
| EECON2 | 0X9D | |
| VRCON | 0X9F | Voltage Reference Control Register |
| C | 0 | Carry/~Borrow Bit-Status Register |
| DC | 1 | Digit Carry/~Borrow Bit-Status Register |
| Z | 2 | Zero Bit-Status Register |
| NOT_PD | 3 | ~Power Down Bit-Status Register |
| NOT_TO | 4 | Time-out Bit-Status Register |
| RP0 | 5 | Register Bank Select Bit-Status Register |
| RA0 | 0 | PORTA pin 0 |
| RA1 | 1 | PORTA pin 1 |
| RA2 | 2 | PORTA pin 2 |
| RA3 | 3 | PORTA pin 3 |
| RA4 | 4 | PORTA pin 4 |
| RA5 | 5 | PORTA pin 5 |
| RA6 | 6 | PORTA pin 6 |
| RA7 | 7 | PORTA pin 7 |
| RB0 | 0 | PORTB pin 0 |
| RB1 | 1 | PORTB pin 1 |
| RB2 | 2 | PORTB pin 2 |
| RB3 | 3 | PORTB pin 3 |
| RB4 | 4 | PORTB pin 4 |
| RB5 | 5 | PORTB pin 5 |
| RB6 | 6 | PORTB pin 6 |
| RB7 | 7 | PORTB pin 7 |
| PS0 | 0 | Prescaler Rate Select Bit 0 - Option Register |
| PS1 | 1 | Prescaler Rate Select Bit 1 - Option Register |
| PS2 | 2 | Prescaler Rate Select Bit 2 - Option Register |
| PSA | 3 | Prescaler Assignment Bit - Option Register |
| T0SE | 4 | TMR0 Source Edge Select Bit - Option Register |
| T0CS | 5 | TMR0 Clock Source Select Bit - Option Register |
| INTEDG | 6 | Interrupt Edge Select Bit - Option Register |
| NOT_RPBU | 7 | ~PORTB Pull-up Enable Bit - Option Register |
| RBIF | 0 | RB Port Change Interrupt Flag Bit - INTCON Register |
| INTF | 1 | External Interrupt Flag Bit - INTCON Register |
| T0IF | 2 | Timer 0 Overflow Interrupt Flag Bit - INTCON Register |
| RBIE | 3 | RB Port Change Interrupt Enable Bit - INTCON Register |
| INTE | 4 | External Interrupt Enable Bit - INTCON Register |
| T0IE | 5 | Timer 0 Overflow Interrupt Enable Bit - INTCON Register |
| PEIE | 6 | Peripheral Interrupt Enable Bit - INTCON Register |
| GIE | 7 | Global Interrupt Enable Bit - INTCON Register |
| RD | 0 | EEPROM Read Control Bit - EECON1 Register |
| WR | 1 | EEPROM Write Control Bit - EECON1 Register |
| WREN | 2 | EEPROM Write Enable Bit - EECON1 Register |
| WRERR | 3 | EEPROM Error Flag Bit - EECON1 Register |
| TRISA0 | 0 | RA0 Input/Output Direction - TRISA Register |
| TRISA1 | 1 | RA1 Input/Output Direction - TRISA Register |
| TRISA2 | 2 | RA2 Input/Output Direction - TRISA Register |
| TRISA3 | 3 | RA3 Input/Output Direction - TRISA Register |
| TRISA4 | 4 | RA4 Input/Output Direction - TRISA Register |
| TRISA5 | 5 | RA5 Input/Output Direction - TRISA Register |
| TRISA6 | 6 | RA6 Input/Output Direction - TRISA Register |
| TRISA7 | 7 | RA7 Input/Output Direction - TRISA Register |
| TRISB0 | 0 | RB0 Input/Output Direction - TRISB Register |
| TRISB1 | 1 | RB1 Input/Output Direction - TRISB Register |
| TRISB2 | 2 | RB2 Input/Output Direction - TRISB Register |
| TRISB3 | 3 | RB3 Input/Output Direction - TRISB Register |
| TRISB4 | 4 | RB4 Input/Output Direction - TRISB Register |
| TRISB5 | 5 | RB5 Input/Output Direction - TRISB Register |
| TRISB6 | 6 | RB6 Input/Output Direction - TRISB Register |
| TRISB7 | 7 | RB7 Input/Output Direction - TRISB Register |
| TMR1IE | 0 | Timer 1 Overflow Interrupt Enable Bit-PIE1 Register |
| TMR2IE | 1 | Timer 2 Overflow Interrupt Enable Bit-PIE1 Register |
| CCP1IE | 2 | Comparator 1 Interrupt Enable Bit-PIE1 Register |
| TXIE | 4 | USART Trasmit Interrupt Enable Bit-PIE1 Register |
| TXIE | 4 | USART Trasmit Interrupt Enable Bit-PIE1 Register |
| RCIE | 5 | USART Receive Interrupt Enable Bit-PIE1 Register |
| CMIE | 6 | Comparator Interrupt Enable Bit-PIE1 Register |
| EEIE | 7 | EE Write Complete Enable Bit-PIE1 Register |
| TMR1IF | 0 | Timer 1 Overflow Interrupt Flag Bit-PIR1 Register |
| TMR2IF | 1 | Timer 2 Overflow Interrupt Flag Bit-PIR1 Register |
| CCP1IF | 2 | Comparator 1 Interrupt Flag Bit-PIR1 Register |
| TXIF | 4 | USART Transmit Interrupt Flag Bit-PIR1 Register |
| RCIF | 5 | USART Receive Interrupt Flag Bit-PIR1 Register |
| CMIF | 6 | Comparator Interrupt Flag Bit-PIR1 Register |
| EEIF | 7 | EEPROM Write Interrupt Flag Bit-PIR1 Register |
| NOT_BOR | 0 | ~Brown-out Reset Status Bit-PCON Register |
| NOT_POR | 1 | ~Power-on Reset Status Bit-PCON Register |
| OSCF | 3 | ~Internal Oscillator Frequency Bit-PCON Register |
| TMR1ON | 0 | Timer 1 On Bit-T1CON Register |
| TMR1CS | 1 | Timer 1 Clock Source Select Bit-T1CON Register |
| TMR1CS | 2 | ~Timer 1 External Clock Input Synchronization Bit-T1CON Register |
| T1OSCEN | 3 | Timer 1 Oscillator Enable Control Bit-T1CON Register |
| T1CKPS0 | 4 | Timer 1 Clock Prescale Select Bit 0-T1CON Register |
| T1CKPS1 | 5 | Timer 1 Clock Prescale Select Bit 1-T1CON Register |
| T2CKPS0 | 0 | Timer 2 Clock Prescale Select Bit 0-T2CON Register |
| T2CKPS1 | 1 | Timer 2 Clock Prescale Select Bit 1-T2CON Register |
| TMR2ON | 2 | Timer 2 On Bit-T2CON Register |
| TOUTPS0 | 3 | Timer 2 Postcale Select Bit 0-T2CON Register |
| TOUTPS1 | 4 | Timer 2 Postcale Select Bit 1-T2CON Register |
| TOUTPS2 | 5 | Timer 2 Postcale Select Bit 2-T2CON Register |
| TOUTPS3 | 6 | Timer 2 Postcale Select Bit 3-T2CON Register |
| CCP1M0 | 0 | CCPx Mode Select Bit 0-CCP1CON Register |
| CCP1M1 | 1 | CCPx Mode Select Bit 1-CCP1CON Register |
| CCP1M2 | 2 | CCPx Mode Select Bit 2-CCP1CON Register |
| CCP1M3 | 3 | CCPx Mode Select Bit 3-CCP1CON Register |
| CCP1Y | 4 | PWM Least Significant Bits Y-CCP1CON Register |
| CCP1X | 5 | PWM Least Significant Bits X-CCP1CON Register |
| CM0 | 0 | Comparator Mode Bit 0-CMCON Register |
| CM1 | 1 | Comparator Mode Bit 1-CMCON Register |
| CM2 | 2 | Comparator Mode Bit 2-CMCON Register |
| CIS | 3 | Comparator Input Switch Bit-CMCON Register |
| C1INV | 4 | Comparator 1 Output Inversion Bit-CMCON Register |
| C2INV | 5 | Comparator 2 Output Inversion Bit-CMCON Register |
| C1OUT | 6 | Comparator 1 Output Bit-CMCON Register |
| C2OUT | 7 | Comparator 2 Output Bit-CMCON Register |
| VR0 | 0 | VREF Value Selection Bit 0-VRCON Register |
| VR1 | 1 | VREF Value Selection Bit 1-VRCON Register |
| VR2 | 2 | VREF Value Selection Bit 2-VRCON Register |
| VR3 | 3 | VREF Value Selection Bit 3-VRCON Register |
| VRR | 5 | VREF Range Selection Bit-VRCON Register |
| VROE | 6 | VREF Output Enable Bit-VRCON Register |
| VREN | 7 | VREF Enable Bit-VRCON Register |
| TX9D | 0 | 9th Bit of Transmit Data-TXSTA Register |
| TRMT | 1 | Transmit Shift Register Select Bit-TXSTA Register |
| BRGH | 2 | High Baud Rate Select Bit-TXSTA Register |
| SYNC | 4 | USART Mode Select Bit-TXSTA Register |
| TXEN | 5 | Transmit Enable Bit-TXSTA Register |
| TX9 | 6 | 9-bit Transmit Enable Bit-TXSTA Register |
| CRSR | 7 | Clock Source Select Bit-TXSTA Register |
| RX9D | 0 | 9th Bitof Received Data-RCSTA Register |
| OERR | 1 | Overrun Error Bit-RCSTA Register |
| FERR | 2 | Framing Error Bit-RCSTA Register |
| ADEN | 3 | Address Detect Enable Bit-RCSTA Register |
| CREN | 4 | Continuous Receive Enable Bit-RCSTA Register |
| SREN | 5 | Single Receive Enable Bit-RCSTA Register |
| RX9 | 6 | 9-bit Receive Enable Bit-RCSTA Register |
| SPEN | 7 | Serial Port Enable Bit-RCSTA Register |